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MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3822 group is the 8-bit microcomputer based on the 740 family core technology. The 3822 group has the LCD drive control circuit an 8-channel AD converter, and a Serial I/O as additional functions. The various microcomputers in the 3822 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3822 group, refer to the section on group expansion.
* LCD drive control circuit
Bias ................................................................................... 1/2, 1/3 Duty ............................................................................ 1/2, 1/3, 1/4 Common output .......................................................................... 4 Segment output ......................................................................... 32 2 Clock generating circuit Clock (XIN-XOUT) .................................. Internal feedback resistor Sub-clock (XCIN-XCOUT) .......... Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode .................................................... 4.0 to 5.5 V (at 8MHz oscillation frequency and high-speed selected) In middle-speed mode ................................................ 2.5 to 5.5 V (at 8MHz oscillation frequency and middle-speed selected) In low-speed mode ...................................................... 2.5 to 5.5 V (Extended operating temperature version: 3.0 V to 5.5 V) Power dissipation In high-speed mode ........................................................... 32 mW (at 8 MHz oscillation frequency) In low-speed mode .............................................................. 45 W (at 32 kHz oscillation frequency, at 3 V power source voltage) Operating temperature range ................................... - 20 to 85C (Extended operating temperature version: -40 to 85C)
*
*
FEATURES
* Basic machine-language instructions ....................................... 71 * The minimum instruction execution time ............................ 0.5 s * * * * * * *
(at 8MHz oscillation frequency) Memory size ROM .................................................................. 4 K to 32 K bytes RAM ................................................................. 192 to 1024 bytes Programmable input/output ports ............................................. 49 Software pull-up/pull-down resistors (Ports P0-P7 except Port P40) Interrupts .................................................. 17 sources, 16 vectors (includes key input interrupt) Timers ........................................................... 8-bit ! 3, 16-bit ! 2 Serial I/O1 ..................... 8-bit ! 1 (UART or Clock-synchronized) Serial I/O2 ........................................................ 8-bit ! 8 channels
*
*
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
SEG8 SEG9 SEG10 SEG11 P34/SEG12 P35/SEG13 P36/SEG14 P37/SEG15 P00/SEG16 P01/SEG17 P02/SEG18 P03/SEG19 P04/SEG20 P05/SEG21 P06/SEG22 P07/SEG23 P10/SEG24 P11/SEG25 P12/SEG26 P13/SEG27 P14/SEG28 P15/SEG29 P16/SEG30 P17/SEG31
SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
M38223M4-XXXFP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P70/XCOUT P71/XCIN RESET P40 P41/
VL2 VL1 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/ADT P56/ TOUT P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45/ TXD P44/RXD P43/INT1 P42/INT0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Package type : 80P6N-A 80-pin plastic-molded QFP
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
SEG10 SEG11 P34/SEG12 P35/SEG13 P36/SEG14 P37/SEG15 P00/SEG16 P01/SEG17 P02/SEG18 P03/SEG19 P04/SEG20 P05/SEG21 P06/SEG22 P07/SEG23 P10/SEG24 P11/SEG25 P12/SEG26 P13/SEG27 P14/SEG28 P15/SEG29
SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 VL1
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
M38223M4-XXXGP M38223M4-XXXHP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P16/SEG30 P17/SEG31 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P70/XCOUT P71/XCIN RESET P40 P41/ P42/INT0 P43/INT1
Package type : 80P6S-A/80P6D-A 80-pin plastic-molded QFP
2
P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/ADT P56/ TOUT P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45/ TXD P44/RXD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6S-A)
Clock input XIN Reset input RESET (5 V) VCC (0 V) VSS
30 71 25
Clock output XOUT
28
29
Data bus
Clock generating circuit CPU A ROM
LCD display RAM (16 bytes)
RAM
X Y S PCH PS Timer X(16) Timer Y(16) Timer 1(8) Timer 2(8) Timer 3(8) PCL
80 79 78 77 76
VL1 VL2 VL3
XCIN Subclock input
XCOUT Subclock output
LCD drive control circuit
75 74 70 69 68 67 66 65 64 63 62 61 60 59
COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11
A-D converter(8)
SI/O(8) TOUT CNTR0,CNTR1 RTP0,RTP1
XCOUT XCIN ADT INT2,INT3 INT0,INT1 P5(8) P4(8)
26 27 9 10 11 12 13 14 15 16
12345678
72 73
17 18 19 20 21 22 23 24
Key-on wake up P3(8) P2(8)
P7(2)
Real time port function
P6(8)
P1(8)
P0(8)
55 56 57 58
31 32 33 34 35 36 37 38
39 40 41 42 43 44 45 46
47 48 49 50 51 52 53 54
3822 Group
I/O port P7
I/O port P6
VREF AVSS (0 V) I/O port P5
I/O port P4
Input port P3
I/O port P2
I/O port P1
I/O port P0
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin VCC, VSS VREF AVSS RESET XIN XOUT Name Power source Analog reference voltage Analog power source Reset input Clock input Clock output Function * Apply voltage of 2.5 V to 5.5 V to VCC, and 0 V to VSS. * Reference voltage input pin for A-D converter. * GND input pin for A-D converter. * Connect to VSS. *Reset input pin for active "L" * Input and output pins for the main clock generating circuit. * Feedback resistor is built in between XIN pin and XOUT pin. * Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. * If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * This clock is used as the oscillating source of system clock. * Input 0 VL1 VL2 VL3 VCC voltage * Input 0 - VL3 voltage to LCD * LCD common output pins * COM2 and COM3 are not used at 1/2 duty ratio. * COM3 is not used at 1/3 duty ratio. * LCD segment output pins 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each port to be individually programmed as either input or output. * Pull-down control is enabled. * * * * 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * 4-bit Input port * CMOS compatible input level * Pull-down control is enabled. * 1-bit input pin * CMOS compatible input level * * * * 7-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * clock output pin * Interrupt input pins * Serial I/O1 function pins * * * * * LCD segment pins Function except a port function
VL1 - VL3 COM0 - COM3
LCD power source Common output
SEG0 - SEG11 P00/SEG16 - P07/SEG23 P10/SEG24 - P17/SEG31 P20 - P27
Segment output I/O port P0
I/O port P1
I/O port P2
* Key input (key-on wake up) interrupt input pins
P30/SEG12 - P37/SEG15 P40 P41/ P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK, P47/SRDY
Input port P3
* LCD segment pins
Input port P4 I/O port P4
4
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR0, P55/CNTR1 * Timer output pin P56/TOUT * A-D trigger input pin P57/ADT P60/AN0P67/AN7 I/O port P6 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * * * * 2-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * * * * * A-D conversion input pins Name I/O port P5 * * * * Function Function except a port function 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * Interrupt input pins * Real time port function pins * Timer function pins
P70/XCOUT, P71/XCIN
I/O port P7
* Sub-clock generating circuit I/O pins (Connect a resonator. External clock cannot be used.)
5
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product M3822 3 M 4 - XXX FP Package type FP : 80P6N-A package GP : 80P6S-A package HP : 80P6D-A package FS : 80D0 package ROM number Omitted in some types. Normally, using hyphen When electrical characteristic, or division of quality identification code using alphanumeric character - : Standard D : Extended operating temperature version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes
6
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 3822 group as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions (2) ROM/PROM size .......................................... 8 K to 16 K bytes RAM size ....................................................... 384 to 512 bytes
(3) Packages 80P6N-A ............................. 0.8 mm-pitch plastic molded QFP 80P6S-A ........................... 0.65 mm-pitch plastic molded QFP 80P6D-A ............................. 0.5 mm-pitch plastic molded QFP 80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Expansion Plan
ROM size (bytes) 32K
28K
24K
20K Mass product 16K M38223M4/E4
12K Mass product 8K M38223M2
4K
192 256
384
512 RAM size (bytes)
640
768
896
1024
Currently supported products are listed below. Product M38223M4-XXXFP M38223E4-XXXFP M38223E4FP M38223M4-XXXGP M38223E4-XXXGP M38223E4GP M38223M4-XXXHP M38223E4-XXXHP M38223E4HP M38223E4FS M38222M2-XXXFP M38222M2-XXXGP M38222M2-XXXHP (P) ROM size (bytes) ROM size for User in ( ) RAM size (bytes) Package Remarks Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version
As of May 1996
80P6N-A
16384 (16254)
512
80P6S-A
80P6D-A 80D0 80P6N-A 80P6S-A 80P6D-A
8192 (8062)
384
7
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION)
Mitsubishi plans to expand the 3822 group (extended operating temperature version) as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions
(2) ROM size ................................................................ 16 K bytes RAM size .................................................................. 512 bytes (3) Packages 80P6N-A ............................. 0.8 mm-pitch plastic molded QFP
Memory Expansion Plan
ROM size (bytes) 32K
28K
24K
20K Under development 16K M38223M4D
12K Mass product 8K M38222M2D
4K
192 256
384
512 RAM size (bytes)
640
768
896
1024
Products under development: the development schedule and specification may be revised without notice.
Currently supported products are listed below. Product M38223M4DXXXFP M38222M2DXXXGP ROM size (bytes) ROM size for User in ( ) 16384(16254) 8192(8062) RAM size (bytes) 512 384 Package 80P6N-A 80P6S-A Mask ROM version Mask ROM version Remarks
As of May 1996
8
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The 3822 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 User's Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used.
CPU Mode Register
The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit and the internal system clock selection bit.
b7
b0 CPU mode register (CPUM (CM) : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area Not used (returns "1" when read) (Do not write "0" to this bit) Port XC switch bit 0 : I/O port 1 : XCIN, XCOUT Main clock ( XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0 : XIN-XOUT selected (middle-/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)
Fig. 1 Structure of CPU mode register
9
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Special Page ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 XXXX16 Reserved area 044016 ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 ROM FF0016 FFDC16 Interrupt vector area FFFE16 Reserved ROM area FFFF16 Special page ZZZZ16 YYYY16 Reserved ROM area (128 bytes) Not used RAM 000016 SFR area 004016 005016 010016 LCD display RAM area Zero page
Fig. 2 Memory map diagram
10
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Port P7 (P7) 000F16 Port P7 direction register (P7D) 001016 001116 001216 001316 001416 001516 001616 PULL register A (PULLA) 001716 PULL register B (PULLB) 001816 Transmit/Receive buffer register(TB/RB) 001916 Serial I/O1 status register (SIO1STS) 001A16 Serial I/O1 control register (SIO1CON) 001B16 UART control register (UARTCON) 001C16 Baud rate generator (BRG) 001D16 001E16 001F16
002016 Timer X (low) (TXL) 002116 Timer X (high) (TXH) 002216 Timer Y (low) (TYL) 002316 Timer Y (high) (TYH) 002416 Timer 1 (T1) 002516 Timer 2 (T2) 002616 Timer 3 (T3) 002716 Timer X mode register (TXM) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 002A16 output control register (CKOUT) 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 A-D control register (ADCON) 003516 A-D conversion register (AD) 003616 003716 003816 Segment output enable register (SEG) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1(IREQ1) 003D16 Interrupt request register 2(IREQ2) 003E16 Interrupt control register 1(ICON1) 003F16 Interrupt control register 2(ICON2)
Fig.3 Memory map of special function register (SFR)
11
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS Direction Registers (ports P2, P41-P47, and P5-P7)
The 3822 group has 49 programmable I/O pins arranged in seven I/O ports (ports P0-P2 and P41-P47 and P5-P7). The I/O ports P2, P41-P47, and P5-P7 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
b7
b0
PULL register A (PULLA : address 001616) P00-P07 pull-down P10-P17 pull-down P20-P27 pull-up P30-P37 pull-down P70, P71 pull-up Not used (return "0" when read)
b7
b0 PULL register B (PULLB : address 001716) P41-P43 pull-up P44-P47 pull-up P50-P53 pull-up P54-P57 pull-up P60, P63 pull-up P64-P67 pull-up Not used (return "0" when read) 0 : Disable 1 : Enable
Direction Registers (ports P0 and P1)
Ports P0 and P1 have direction registers which determine the input /output direction of each individual port. Each port in a direction register corresponds to one port, each port can be set to be input or output. When "0" is written to the bit 0 of a direction register, that port becomes an input port. When "1" is written to that port, that port becomes an output port. Bits 1 to 7 of ports P0 and P1 direction registers are not used.
Note : The contents of PULL register A and PULL register B do not affect ports programmed as the output ports.
Fig. 4 Structure of PULL register A and PULL register B
Ports P3 and P40
These ports are only for input.
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL register B (address 001716), ports except for port P40 can control either pull-down or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports.
12
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pin P00/SEG16- P07/SEG23 P10/SEG24- P17/SEG31
Name Port P0
Input/Output Input/output, individual ports Input/output, individual ports Input/output, individual bits
Port P1
P20 - P27
Port P2
I/O Format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level
Non-Port Function LCD segment output
LCD segment output Key input(Key-on wake up) interrupt input LCD segment output
P34/SEG12- P37/SEG15 P40 P41/
Port P3
Input
Related SFRs PULL register A Segment output enable register PULL register A Segment output enable register PULL register A Interrupt control register 2 PULL register A Segment output enable register PULL register B output control register PULL register B Interrupt edge selection register PULL register B Serial I/O control register Serial I/O status register UART control register
Diagram No.
(1)
(2)
(3) (4)
clock output
(5)
P42/INT0, P43/INT1 P44/RXD P45/TXD P46/SCLK1 P47/SRDY P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR0 P55/CNTR1 P56/TOUT P57/ADT P60/AN0- P67/AN7 P70/XCOUT P71/XCIN COM0-COM3 SEG0-SEG11
Port P4
External interrupt input
(2) (6) (7) (8) (9) (2)
Serial I/O function I/O
Input/output, individual bits Port P5
CMOS compatible input level CMOS 3-state output
External interrupt input Real time port function oputput
PULL register B Interrupt edge selection register
(10)
Timer I/O Timer I/O Timer output A-D trigger input
Port P6 Port P7 Common Segment output LCD common output LCD segment output
A-D conversion input Sub-clock generating circuit I/O
PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B Timer 123 mode register PULL register B A-D control register PULL register A CPU mode register LCD mode register Segment output enable register
(11) (12) (13) (12) (14) (15) (16) (17) (18)
Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
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MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1)Ports P0, P1 VL2/VL3
(2)Ports P2, P42, P43, P50, P51 Pull-up control
VL1/VSS Segment output enable bit (Note) Direction register Data bus Data bus Port latch Direction register Port latch
Key input (Key-on wake up) interrupt input INT0-INT3 interrupt input Pull-down control Segment output enable bit Note : Bit 0 of direction register (3)Ports P34-P37 VL2/VL3 Data bus VL1/VSS (4)Port P40
Pull-down control Segment output enable bit (6)Port P44 Pull-up control Serial I/O enable bit Reception enable bit Direction register Data bus Direction register Data bus Port latch Pull-up control
(5)Port P41
Port latch
output control bit
Serial I/O input
Fig. 5 Port block diagram (1)
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MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(7)Port P45
(8)Port P46 Serial I/O clock-synchronized selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch
Pull-up control P45/TXD P-channel output disable bit Serial I/O enable bit Transmission enable bit Direction register Data bus Port latch
Pull-up control
Serial I/O output
Serial I/O clock output Serial I/O clock input
(9) Port P47 Pull-up control
(10)Ports P52, P53 Pull-up control
Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Data bus Port latch
Direction register Data bus
Port latch
Serial I/O ready output
Real time port control bit Date for real time port
(11) Port P54 Pull-up control
(12) Ports P55, P57 Pull-up control Direction register Direction register
Data bus
Port latch Data bus Port latch
Timer X operating mode bit (Pulse output mode selection) Timer output CNTR0 interrupt input CNTR1 interrupt input A-D trigger interrupt input
Fig. 6 Port block diagram (2)
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MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(13) Port P56 Pull-up control
(14) Port P6 Pull-up control
Direction register Data bus Data bus
Direction register
Port latch
Port latch
TOUT output control bit Timer output
A-D conversion input Analog input pin selection bit
(15) Port P70 Port selection/Pull-up control Port XC switch bit Direction register Data bus Port latch
(16) Port P71 Port selection/Pull-up control Port XC switch bit Direction register Data bus Port latch
Oscillation circuit Port P71 Port XC switch bit Sub-clock generating circuit input
(17) COM0-COM3 VL3
(18) SEG0-SEG11 VL2/VL3 The voltage applied to the sources of P-channel and N-channel transistors is the controlled voltage by the bias value.
VL2 VL1
The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. VSS
VL1/VSS
Fig. 7 Port block diagram (3)
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MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight internal, and one software.
Interrupt Operation
When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to inhibit other interrupts from interfering.The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt.
Notes on Use
When the active edge of an external interrupt (INT0-INT3, CNTR0, or CNTR1) is changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to "0". (4) Enable the external interrupt which is selected.
Table 1. Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1 Serial I/O reception Serial I/O transmission Timer X Timer Y Timer 2 Timer 3 CNTR0 CNTR1 Timer 1 INT2 INT3 Key input (Key-on wake up) ADT 16 A-D conversion BRK instruction 17 FFDD16 FFDC16 FFDF16 FFDE16 At completion of A-D conversion At BRK instruction execution Priority 1 2 3 4 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFF916 FFF716 FFFA16 FFF816 FFF616 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O data reception At completion of serial I/O transmit shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At falling of conjunction of input level for port P2 (at input mode) At falling of ADT input Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected
5 6 7 8 9 10 11 12 13 14 15
FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116
FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016
Valid when serial I/O1 is selected
External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid when an "L" level is applied) Valid when ADT interrupt is selected External interrupt (valid at falling) Valid when A-D interrupt is selected Non-maskable software interrupt
Notes 1 : Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority.
17
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Interrupt request
Fig. 8 Interrupt control
b7
b0
Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active
Not used (return "0" when read)
b7
b0
Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit
b7
b0
Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (returns "0" when read)
0 : No interrupt request issued 1 : Interrupt request issued
b7
b0
Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit
b7 0
b0
Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit)
0 : Interrupts disabled 1 : Interrupts enabled
Fig. 9 Structure of interrupt-related registers
18
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-on Wake Up)
A Key input interrupt request is generated by applying "L" level to any pin of port P2 that have been set to input mode. In other words, it is generated when AND of input level goes from "1" to "0".
An example of using a key input interrupt is shown in Figure 10, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20-P23.
Port PXx "L" level output PULL register A Bit 2 = "1" Port P27 direction register = "1" Port P27 latch
Key input interrupt request
V P27 output
VV
V P26 output
VV
Port P26 direction register = "1" Port P26 latch
V P25 output
VV
Port P25 direction register = "1" Port P25 latch
V P24 output
VV
Port P24 direction register = "1" Port P24 latch
V P23 input
VV
Port P23 direction register = "0" Port P23 latch
Port P2 Input reading circuit
V P22 input
VV
Port P22 direction register = "0" Port P22 latch
V P21 input
VV
Port P21 direction register = "0" Port P21 latch
V P20 input
VV
Port P20 direction register = "0" Port P20 latch
V P-channel transistor for pull-up VV CMOS output buffer
Fig. 10 Connection example when using key input interrupt and port P2 block diagram
19
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 3822 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches "0016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1".
Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation.
Real time port control bit "1" P60 QD P60 data for real time port Latch P60 direction register "0" P60 latch Real time port control bit "1" QD P61 Latch P61 direction register "0" P61 latch
Data bus
P61 data for real time port Real time port control bit "0" "1"
Timer X mode register write signal Timer X write control bit
Timer X (high) latch (8) Timer X (high) (8)
f(XIN)/16 (f(XCIN)/16 in low-speed mode V) CNTR0 active edge switch bit "0"
Timer X operating mode bit "00","01","11"
Timer X stop control bit
Timer X (low) latch (8) Timer X (low) (8)
P54/CNTR0
"10" "1" Pulse width measurement mode CNTR0 active edge switch bit "0" "1" P54 direction register P54 latch Pulse output mode
Timer X interrupt request CNTR0 interrupt request
Pulse output mode QS T Q
Rising edge detection Falling edge detection Period measurement mode
Timer Y operating mode bit "00","01","10"
Pulse width HL continuously measurement mode
CNTR1 interrupt request
"11"
P55/CNTR1
CNTR1 active edge switch bit "0" "1"
f(XIN)/16 (f(XCIN)/16 in low-speed mode V) Timer Y stop control bit "00","01","11"
Timer Y (low) latch (8) Timer Y (low) (8) Timer Y (high) latch (8) Timer Y (high) (8)
"10" Timer Y operating mode bit
Timer Y interrupt request
f(XIN)/16 (f(XCIN)/16 in low-speed mode V) Timer 1 count source selection bit "0" Timer 1 latch (8) XCIN Timer 1 (8) "1"
Timer 2 count source selection bit Timer 2 latch (8) "0" Timer 2 (8) "1"
f(XIN)/16 (f(XCIN)/16 in low-speed modeV)
Timer 2 write control bit
Timer 1 interrupt request Timer 2 interrupt request
TOUT output active edge switch bit "0" P56/TOUT
TOUT output control bit QS Timer 3 latch (8) Timer 3 (8) "1" Timer 3 count source selection bit
T "1" Q P56 latch P56 direction register TOUT output control bit f(XIN)/16(f(XCIN)/16 in low-speed mode V)
"0"
Timer 3 interrupt request
VInternal
clock = XCIN/2.
Fig. 11 Timer block diagram
20
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). Pulse output mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to output mode. Event counter mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to input mode. Pulse width measurement mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR0 active edge switch bit is "0", the timer counts while the input signal of CNTR0 pin is at "H". If it is "1", the timer counts while the input signal of CNTR0 pin is at "L". When using a timer in this mode, set the corresponding port P54 direction register to input mode.
Note on CNTR0 Interrupt Active Edge Selection
CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit.
Real Time Port Control
While the real time port function is valid, data for the real time port are output from ports P52 and P53 each time the timer X underflows. (However, after rewriting a data for real time port, if the real time port control bit is changed from "0" to "1", data are output without the timer X.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode.
b7
b0 Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid P52 data for real time port P53 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Count at rising edge in event counter mode Start from "H" output in pulse output mode Measure "H" pulse width in pulse width measurement mode Falling edge active for CNTR0 interrupt 1 : Count at falling edge in event counter mode Start from "L" output in pulse output mode Measure "L" pulse width in pulse width measurement mode Rising edge active for CNTR0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop
Timer X Write Control
If the timer X write control bit is "0", when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is "1", when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing.
Fig. 12 Structure of timer X mode register
21
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes. Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). Period measurement mode CNTR1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down/Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR1 pin input signal is found by CNTR1 interrupt. When using a timer in this mode, set the corresponding port P55 direction register to input mode. Event counter mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode. Pulse width HL continuously measurement mode CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode.
b7 b0 Timer Y mode register (TYM : address 002816) Not used (return "0" when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop
Fig. 13 Structure of timer Y mode register
Note on CNTR1 Interrupt Active Edge Selection
CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit.
22
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed.
b7 b0 Timer 123 mode register (T123M : address 002916) TOUT output active edge switch bit 0 : Start at "H" output 1 : Start at "L" output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (return "0" when read) Note : Internal clock is f(XCIN)/2 in the low-speed mode.
Timer 2 Write Control
If the timer 2 write control bit is "0", when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is "1", when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows.
Timer 2 Output Control
When the timer 2 (TOUT) is output enabled, an inversion signal from pin TOUT is output each time timer 2 underflows. In this case, set the port P56 shared with the port TOUT to the output mode.
Note on Timer 1 to Timer 3
When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer . If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3.
Fig. 14 Structure of timer 123 mode register
23
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation.
Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 001816).
Data bus Address 001816
Receive buffer Serial I/O control register
Address 001A16
Receive buffer full flag (RBF) Receive interrupt request (RI)
Clock control circuit
P44/RXD
Receive shift register
Shift clock P46/SCLK1
f(XIN)
BRG count source selection bit 1/4
Serial I/O synchronization clock selection bit Frequency division ratio 1/(n+1)
Baud rate generator
1/4
Address 001C16
Falling-edge detector Clock control circuit
P47/SRDY1
F/F
Shift clock P45/TXD
Transmit shift register
Transmit buffer register (TB)
Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Serial I/O transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 001916
Serial I/O status register
Address 001816 Data bus
Fig. 15 Block diagram of clock synchronous serial I/O
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD Serial input RXD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY1 Write signal to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 16 Operation of clock synchronous serial I/O function
24
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Asynchronous Serial I/O1 (UART) Mode
Clock asynchronous serial I/O1 mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
Data bus Address 001816 Serial I/O control register Address 001A16 Receive buffer full flag (RBF)
Serial I/O receive interrupt request (RI)
Receive buffer register(RB) OE Character length selection bit
P44/RXD
ST detector
7 bits 8 bits
Receive shift register 1/16 PE FE SP detector Clock control circuit UART control register Address 001B16
Serial I/O synchronization clock selection bit P46/SCLK1 BRG count source selection bit 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16
ST/SP/PA generator
f(XIN)
1/16 P45/TXD Character length selection bit
Transmit buffer register
Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 001916
Transmit shift register
Address 001816 Data bus
Fig. 17 Block diagram of UART serial I/O
Transmit or receive clock Transmit buffer register write signal TBE=0 TSC=0 TBE=1 Serial output TXD ST D0 TBE=0 TBE=1 D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1
VGenerated
TSC=1V SP at 2nd bit in 2-stop-bit mode
Receive buffer register read signal
RBF=1 Serial input RXD ST D0 D1 SP ST D0
RBF=0
RBF=1
D1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes "1". 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 18 Operation of UART serial I/O function
25
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O Control Register (SIO1CON) 001A16
The serial I/O control register contains eight control bits for the serial I/O function.
UART Control Register (UARTCON) 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/TXD pin.
Serial I/O Status Register (SIO1STS) 001916
The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1".
Transmit Buffer/Receive Buffer Register (TB/ RB) 001816
The transmit buffer register and the receive buffer are located at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is "0".
Baud Rate Generator (BRG) 001C16
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
26
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE) =0 1: (OE) U (PE) U (FE) =1 Not used (returns "1" when read)
b7
b0
Serial I/O control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronization clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronized serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronized serial I/O is selected. External clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P44-P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P44-P47 operate as serial I/O pins)
b7
b0
UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return "1" when read)
Fig. 19 Structure of serial I/O control registers
27
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The functional blocks of the A-D converter are described below.
Comparator and Control Circuit
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Note that the comparator is constructed linked to a capacitor, so set f(XIN) to at least 500 kHz during A-D conversion.
A-D Conversion Register (AD) 003516
The A-D conversion register is a read-only register that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read.
A-D Control Register (ADCON) 003416
The A-D control register controls the A-D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion, then changes to "1" when the A-D conversion is completed. Writing "0" to this bit starts the A-D conversion. Bit 4 controls the transistor which breaks the through current of the resistor ladder. When bit 5, which is the AD external trigger valid bit, is set to "1", this bit enables A-D conversion even by a falling edge of an ADT input. Set ports which share with ADT pins to input when using an A-D external trigger.
b7
b0
A-D control register (ADCON : address 003416) Analog input pin selection bits 0 0 0 : P60/AN0 0 0 1 : P61/AN1 0 1 0 : P62/AN2 0 1 1 : P63/AN3 1 0 0 : P64/AN4 1 0 1 : P65/AN5 1 1 0 : P66/AN6 1 1 1 : P67/AN7 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF input switch bit 0 : OFF 1 : ON AD external trigger valid bit 0 : A-D external trigger invalid 1 : A-D external trigger valid Interrupt source selection bit 0 : Interrupt request at A-D conversion completed 1 : Interrupt request at ADT input falling Not used (returns "0" when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P67/AN7 to P60/AN0.
Fig. 20 Structure of A-D control register
Data bus
b7 A-D control register P57/ADT 3
b0
A-D control circuit P60/AN0
Channel selector
ADT/A-D interrupt request
P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7
Comparator
A-D conversion register 8 Resistor ladder
AVSS
VREF
Fig. 21 A-D converter block diagram
28
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD DRIVE CONTROL CIRCUIT
The 3822 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. LCD display RAM Segment output enable register LCD mode register Selector Timing controller Common driver Segment driver Bias control circuit A maximum of 32 segment output pins and 4 common output pins can be used. Up to 128 pixels can be controlled for LCD display. When the LCD enable bit is set to "1" after data is set in the LCD mode register,
* * * * * * * *
the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 2. Maximum number of display pixels at each duty ratio Duty ratio 2 3 4 Maximum number of display pixel 64 dots or 8 segment LCD 8 digits 96 dots or 8 segment LCD 12 digits 128 dots or 8 segment LCD 16 digits
b7
b0 Segment output enable register (SEG : address 003816) Segment output enable bit 0 0 : Input ports P34-P37 1 : Segment output SEG12-SEG15 Segment output enable bit 1 0 : I/O ports P00, P01 1 : Segment output SEG16,SEG17 Segment output enable bit 2 0 : I/O ports P02-P07 1 : Segment output SEG18-SEG23 Segment output enable bit 3 0 : I/O ports P10,P11 1 : Segment output SEG24,SEG25 Segment output enable bit 4 0 : I/O port P12 1 : Segment output SEG26 Segment output enable bit 5 0 : I/O ports P13-P17 1 : Segment output SEG27-SEG31 Not used (return "0" when read) (Do not write "1" to this bit)
b7
b0 LCD mode register (LM : address 003916) Duty ratio selection bits 0 0 : Not available 0 1 : 2 (use COM0,COM1) 1 0 : 3 (use COM0-COM2) 1 1 : 4 (use COM0-COM3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Not used (returns "0" when read) (Do not write "1" to this bit) LCD circuit divider division ratio selection bits 0 0 : CLOCK input 0 1 : 2 division of CLOCK input 1 0 : 4 division of CLOCK input 1 1 : 8 division of CLOCK input LCDCK count source selection bit (Note) 0 : f(XCIN)/32 1 : f(XIN)/8192 Note : LCDCK is a clock for a LCD timing controller.
Fig. 22 Structure of segment output enable register and LCD mode register
29
30
LCD enable bit Address 004F16 LCD display RAM LCD circuit divider division ratio selection bits 2 Bias control bit LCD divider 2 Duty ratio selection bits LCDCK count source selection bit "1" f(XIN)/8192 f(XCIN)/32 "0" Selector Selector Timing controller LCDCK Segment Segment driver driver Bias control
Common driver Common driver Common driver Common driver
Data bus
Fig. 23 Block diagram of LCD controller/driver
Address 004016
Address 004116
Selector Selector Selector Selector
Segment Segment Segment Segment driver driver driver driver
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SEG0 P34/SEG12
SEG1
SEG2
SEG3
P16/SEG30 P17/SEG31
VSS VL1 VL2 VL3
COM0 COM1 COM2 COM3
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bias Control and Applied Voltage to LCD Power Input Pins
To the LCD power input pins (VL1-VL3), apply the voltage shown in Table 3 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register).
Table 3. Bias control and applied voltage to VL1-VL3 Bias value 1/3 bias VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD VL3=VLCD VL2=VL1=1/2 VLCD Voltage value
1/2 bias
Common Pin and Duty Ratio Control
The common pins (COM0-COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register).
Note 1 : VLCD is the maximum value of supplied voltage for the LCD panel. Table 4. Duty ratio control and common pins used Duty ratio 2 3 4 Duty ratio selection bit Bit 1 0 1 1 Bit 0 1 0 1 Common pins used COM0, COM1 (Note 1) COM0-COM2 (Note 2) COM0-COM3
Notes 1 : COM2 and COM3 are open 2 : COM3 is open
Contrast control
Contrast control
VL3 R1 VL2 R2 VL1 R3
VL3 R4 VL2
VL1 R5
1/3 bias
R1 = R2 = R3
1/2 bias
R4 = R5
Fig. 24 Example of circuit at each bias
31
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD Display RAM
Address 004016 to 004F16 is the designated RAM for the LCD display. When "1" are written to these addresses, the corresponding segments of the LCD display panel are turned on.
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation; f(LCDCK)= (frequency of count source for LCDCK) (divider division ratio for LCD) f(LCDCK) duty ratio
Frame frequency=
Bit 7 Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 SEG1 SEG0 SEG3 SEG2 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG25 SEG27 SEG29 SEG31 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 SEG26 SEG28 SEG30 6 5 4 3 2 1 0
Fig. 25 LCD display RAM map
32
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic LCDCK timing
1/4 duty
Voltage level VL3 VL2=VL1 VSS
COM0 COM1 COM2 COM3 SEG0
VL3 VSS
OFF COM3 COM2 COM1
ON COM0 COM3
OFF COM2 COM1
ON COM0
1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2=VL1 VSS
SEG0
ON COM0 1/2 duty COM0 COM1 SEG0
OFF COM2 COM1
ON COM0
OFF COM2 COM1
ON COM0
OFF COM2
VL3 VL2=VL1 VSS
VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0
Fig. 26 LCD drive waveform (1/2 bias)
33
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic LCDCK timing
1/4 duty
Voltage level VL3 VL2 VL1 VSS
COM0
COM1 COM2 COM3 SEG0 VL3 VSS
OFF COM3 COM2 COM1
ON COM0 COM3
OFF COM2 COM1
ON COM0
1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2 VL1 VSS
SEG0
ON COM0 1/2 duty COM0 COM1 SEG0
OFF COM2 COM1
ON COM0
OFF COM2 COM1
ON COM0
OFF COM2
VL3 VL2 VL1 VSS
VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0
Fig. 27 LCD drive waveform (1/3 bias)
34
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK OUTPUT FUNCTION
The internal system clock can be output from port P41 by setting the output control register. Set bit 1 of the port P4 direction register to when outputting clock.
b7
b0 output control register (CKOUT : address 002A16)
output control bit 0 : Port function 1 : clock output Not used (return "0" when read)
Fig. 28 Structure of output control register
35
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 2.5 V and 5.5 V, and the oscillation should be stable), reset is released. In order to give the XIN clock time to stabilize, internal operation does not begin until after 8200 XIN clock cycles (timer 1 and timer 2 are connected together and 512 cycles of f(XIN)/16) are complete. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.5 V for VCC of 2.5 V (Extended operating temperature version: the reset input voltage is less than 0.6V for VCC of 3.0V).
Address ( 1 ) Port P0 direction register (000116) * * * ( 2 ) Port P1 direction register (000316) * * * ( 3 ) Port P2 direction register (000516) * * * ( 4 ) Port P4 direction register (000916) * * * ( 5 ) Port P5 direction register (000B16) * * * ( 6 ) Port P6 direction register (000D16) * * * ( 7 ) Port P7 direction register (000F16) * * * ( 8 ) PULL register A ( 9 ) PULL register B Register contents 0016 0016 0016 0016 0016 0016 0016
(001616) * * * 0 0 0 0 1 0 1 1 (001716) * * * 0016
(10) Serial I/O status register (001916) * * * 1 0 0 0 0 0 0 0 (11) Serial I/O control register (001A16) * * * (12) UART control register (13) Timer X (low) (14) Timer X (high) 0016
(001B16) * * * 1 1 1 0 0 0 0 0 (002016) * * * (002116) * * * (002216) * * * (002316) * * * (002416) * * * (002516) * * * (002616) * * * (002716) * * * (002816) * * * FF16 FF16 FF16 FF16 FF16 0116 FF16 0016 0016 0016 0016
Power on Power source voltage 0V Reset input voltage 0V (Note)
(15) Timer Y (low) (16) Timer Y (high) (17) Timer 1
RESET
VCC
0.2VCC
(18) Timer 2 (19) Timer 3 (20) Timer X mode register (21) Timer Y mode register
Note. Reset release voltage : VCC = 2.5V (Extended operating temperature version : 3.0V)
RESET
VCC Power source voltage detection circuit
(22) Timer 123 mode register (002916) * * * (23) output control register (002A16) * * * (24) A-D control register (25) Segment output enable register (26) LCD mode register (27) Interrupt edge selection register (28) CPU mode register (29) Interrupt request register 1
(003416) * * * 0 0 0 0 1 0 0 0 (003816) * * * (003916) * * * (003A16) * * * 0016 0016 0016
(003B16) * * * 0 1 0 0 1 0 0 0 (003C16) * * * (003D16) * * * (003E16) * * * (003F16) * * * 0016 0016 0016 0016
Fig. 29 Example of reset circuit
(30) Interrupt request register 2 (31) Interrupt control register 1 (32) Interrupt control register 2 (33) Processor status register (34) Program counter
(PS) ! ! ! ! ! 1 ! ! (PCH) (PCL)
Contents of address FFFD Contents of address FFFC
16
16
Note ! : Undefined The contents of all other registers and RAM are undefined after reset, so they must be initialized by software.
Fig. 30 Internal state of microcomputer after reset
36
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XIN
RESET
Internal reset
Reset address from vector table
Address Data
?
?
?
?
FFFC ADL
FFFD
ADH, ADL ADH
SYNC Notes 1 : f(XIN) and f() are in the relationship : f(XIN) = 8 * f() Notes 2 : A question mark (?) indicates an undefined status that depends on the previous status.
XIN : about 8200 clock cycles
Fig. 31 Reset sequence
37
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 3822 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. The pull-up resistor of XCIN and XCOUT pins must be made invalid to use the sub-clock.
Oscillation Control
Stop mode If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillators stop. Timer 1 is set to "FF16" and timer 2 is set to "0116". Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to "0". Set the timer 1 and timer 2 interrupt enable bits to disabled ("0") before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level. The states of XIN and XCIN are the same as the state before the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
Frequency Control
Middle-speed mode The internal clock is the frequency of XIN divided by 8. After reset, this mode is selected. High-speed mode The internal clock is half the frequency of XIN. Low-speed mode
* The internal clock is half the frequency of XCIN. * A low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to "1". When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming. Note: If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/highspeed and low-speed, set the frequency on condition that f(XIN)>3f(XCIN).
XCIN XCOUT Rf CCIN Rd CCOUT
XIN
XOUT
CIN
COUT
Fig. 32 Ceramic resonator circuit
XCIN Rf CCIN
XCOUT Rd CCOUT
XIN
XOUT Open
External oscillation circuit
VCC VSS
Fig. 33 External clock input circuit
38
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
XCOUT
"1"
"0" Port XC switch bit
XIN
XOUT
Internal system clock selection bit (Note)
Timer 1 count source selection bit "1" Timer 1 "0"
Timer 2 count source selection bit "0" Timer 2 "1"
Low-speed mode "1" 1/2 "0" Middle-/High-speed mode
1/4
1/2
Main clock division ratio selection bit Middle-speed mode Timing (Internal system clock)
High-speed mode or Low-speed mode Main clock stop bit
Q
S R WIT instruction
S R
Q
Q
S STP instruction
STP instruction
R
Reset Interrupt disable flag I Interrupt request
Note : When using the low-speed mode, set the port X C switch bit to "1" .
Fig. 34 Clock generating circuit block diagram
39
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode (f() =1 MHz) CM7 =0(8 MHz selected) CM6 =1(Middle-speed) CM5 =0(8 MHz oscillating) CM4 =0(32 kHz stopped)
CM6 "1"
High-speed mode (f() =4 MHz)
"0"
CM7=0(8 MHz selected) CM6=0(High-speed) CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped)
CM " "1 M6 C " "1
4
"0
" "0 "
CM4 "1"
"
"0
"
Middle-speed mode (f() =1 MHz) CM7 =0(8 MHz selected) CM6 =1(Middle-speed) CM5 =0(8 MHz oscillating) CM4 =1(32 kHz oscillating)
CM6 "1"
High-speed mode (f() =4 MHz)
"0"
CM7=0(8 MHz selected) CM6=0(High-speed) CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating)
"0"
CM7 "1"
Low-speed mode (f() =16 kHz) CM7=1(32 kHz selected) CM6=1(Middle-speed) CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating)
CM6 "1"
Low-speed mode (f() =16 kHz)
"0"
CM7=1(32 kHz selected) CM6=0(High-speed) CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating)
CM7 "1"
"0"
CM4 "1"
C "0 M4 " CM "1 "6 "1
"0"
"0"
b7
b4 CPU mode register (CPUM : address 003B16)
CM " "1 M6 C " "1
5
"0
" " 0"
"1 "
C "0 M5 " CM
6
"0"
"0"
CM5 "1"
"
"0
"
Low-speed mode (f() =16 kHz) CM7=1(32 kHz selected) CM6=1(Middle-speed) CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating)
CM6 "1"
Low-speed mode (f() =16 kHz)
"0"
CM7=1(32 kHz selected) CM6=0(High-speed) CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating)
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3 : Timer and LCD operate in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle-/highspeed mode. 7 : The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the XCIN pin. indicates the internal clock.
Fig. 35 State transitions of internal clock
40
CM5 "1"
"1
CM4 : Port Xc switch bit 0: I/O port 1: XCIN, XCOUT CM5 : Main clock (XIN-XOUT) stop bit 0: Oscillating 1: Stopped CM6 : Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM7 : Internal system clock selection bit 0: XIN-XOUT selected (middle-/high-speed mode) 1: XCIN-XCOUT selected (low-speed mode)
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1". After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1". Serial I/O continues to output the final bit from the TXD pin after transmission is completed.
Interrupt
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is at least 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers.
41
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area.
Package 80P6N-A 80P6S-A 80P6D-A 80D0
Name of Programming Adapter PCA4738F-80A PCA4738G-80 PCA4738H-80 PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 36 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150C for 40 hours)
Verification with PROM programmer
Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours.
Fig. 36 Programming and testing of One Time PROM version
42
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VI VI VI VI VO VO VO VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P34-P37, P40-P47, P50-P57, P60-P67, P70, P71 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN Output voltage P00-P07, P10-P17 Output voltage P34-P37 Output voltage P20-P27, P41-P47, P50-P57, P60-P67, P70, P71 Output voltage SEG0-SEG11 Output voltage XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to 7.0 -0.3 to VCC +0.3 All voltages are based on VSS. Output transistors are cut off. -0.3 to VL2 VL1 to VL3 VL2 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VL3 +0.3 -0.3 to VL3 +0.3 -0.3 to VCC +0.3 -0.3 to VL3 +0.3 -0.3 to VCC +0.3 300 -20 to 85 (Note 1) -40 to 125 (Note 2) Unit V V V V V V V V V V V V mW C C
At output port At segment output At segment output
Ta = 25 C
Notes 1 : Extended operating temperature version : -40 to 85C 2 : Extended operating temperature version : -65 to 150C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter
(VCC = 2.5 to 5.5 V, Ta = -20 to 85C, unless otherwise noted. Limits Typ. 5.0 5.0 5.0 5.0 5.0 0 0 AVSS 0.7 VCC 0.8 VCC 0.8 VCC 0.8 VCC 0 0 0 0 VCC VCC VCC VCC VCC 0.3 VCC 0.2 VCC 0.2 VCC 0.2 VCC
Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5V, Ta = -20 to 85C) Min. 4.0 2.5 3.0 2.5 3.0 2 Max. 5.5 5.5 5.5 5.5 5.5 VCC Unit
VCC
Power source voltage
High-speed mode f(XIN)=8 MHz Middle-speed mode Ta = -20 to 85C f(XIN)=8 MHz Ta = -40 to -20C Low-speed mode Ta = -20 to 85C Ta = -40 to -20C
V
VSS VREF AVSS VIA VIH VIH VIH VIH VIL VIL VIL VIL
Power source voltage A-D conversion reference input voltage Analog power source voltage Analog input voltage AN0-AM7 "H" input voltage P00-P07, P10-P17, P34-P37, P40, P41, P45, P47, P52, P53, P56, P60-P67, P70, P71 (CM4=0) "H" input voltage P20-P27, P42-P44, P46, P50, P51, P54, P55, P57 "H" input voltage RESET "H" input voltage XIN "L" input voltage P00-P07, P10-P17, P34-P37, P40, P41, P45, P47, P52, P53, P56, P60-P67, P70, P71 (CM4=0) "L" input voltage P20-P27, P42-P44, P46, P50, P51, P54, P55, P57 "L" input voltage "L" input voltage RESET XIN
V V V V V V V V V V V V
43
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS (VCC = 2.5 to 5.5 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C)
Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) "H" total peak output current "H" total peak output current "L" total peak output current "L" total peak output current "H" total average output current "H" total average output current "L" total average output current "L" total average output current "H" peak output current "H" peak output current "L" peak output current "L" peak output current "H" average output current "H" average output current "L" average output current "L" average output current Input frequency for timers X and Y (duty cycle 50 %) Parameter P00-P07, P10-P17, P20-P27 (Note 1) P41-P47,P50-P57, P60-P67, P70, P71 (Note 1) P00-P07, P10-P17, P20-P27 (Note 1) P41-P47,P50-P57, P60-P67, P70, P71 (Note 1) P00-P07, P10-P17, P20-P27 (Note 1) P41-P47,P50-P57, P60-P67, P70, P71 (Note 1) P00-P07, P10-P17, P20-P27 (Note 1) P41-P47,P50-P57, P60-P67, P70, P71 (Note 1) P00-P07, P10-P17 (Note 2) P20-P27, P41-P47, P50-P57, P60-P67, P70, P71 (Note 2) P00-P07, P10-P17 (Note 2) P20-P27, P41-P47, P50-P57, P60-P67, P70, P71 (Note 2) P00-P07, P10-P17 (Note 3) P20-P27, P41-P47, P50-P57, P60-P67, P70, P71 (Note 3) P00-P07, P10-P17 (Note 3) P20-P27, P40-P47, P50-P57, P60-P67, P70, P71 (Note 3) 4.0 V VCC 5.5 V 2.5 V VCC 4.0 V Min. Limits Typ. Max. -40 -40 40 40 -20 -20 20 20 -2 -5 5 10 -1.0 -2.5 2.5 5.0 4.0 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz
f(CNTR0) f(CNTR1)
(2XVCC)-4 MHz 8.0 (4XVCC)-8 8.0 32.768 50 MHz MHz MHz kHz
f(XIN) f(XCIN)
High-speed mode (4.0 V VCC 5.5 V) Main clock input oscillation High-speed mode (2.5 V VCC 4.0 V) frequency (Note 4) Middle-speed mode Sub-clock input oscillation frequency (Note 4, 5)
Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2 : The peak output current is the peak current flowing in each port. 3 : The average output current is an average value measured over 100 ms. 4 : When the oscillation frequency has a duty cycle of 50%. 5 : When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
44
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Symbol Parameter
(VCC = 4.0 to 5.5 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Test conditions IOH = -2.5 mA IOH = -0.6 mA VCC = 2.5 V IOH = -5 mA IOH = -1.25 mA IOH = -1.25 mA VCC = 2.5 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 2.5 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 2.5 V Min. VCC-2.0 VCC-1.0 VCC-2.0 VCC-0.5 VCC-1.0 2.0 0.5 1.0 2.0 0.5 1.0 0.5 0.5 0.5 5.0 Ta = -20 to 85C Ta = -40 to -20C Ta = -20 to 85C Ta = -40 to -20C 6.0 30 70 70 25 25 140 170 45 55 5.0 5.0 4.0 -5.0 VI = VSS Pull-ups "off" VCC= 5.0 V, VI = VSS Pull-ups "on" VCC= 3.0 V, VI = VSS Pull-ups "on" VI = VSS VI = VSS -5.0 -30 -6 -70 -25 -140 -45 A A A A A A A A Limits Typ. Max. Unit V V V V V V V V V V V V V V A A
VOH
"H" output voltage P00-P07, P10-P17
VOH
"H" output voltage P20-P27, P41-P47,P50-P57, P60-P67, P70, P71 (Note 1)
VOL
"L" output voltage P00-P07, P10-P17
VOL
"L" output voltage P20-P27, P41-P47, P50-P57, P60-P67, P70, P71 (Note 1) Hysteresis Hysteresis Hysteresis CNTR0, CNTR1, INT0-INT3, P20-P27 RXD, SCLK RESET
VT+ - VT- VT+ - VT- VT+ - VT-
RESET: VCC=2.5 V to 5.5 V VI = VCC Pull-downs "off" VCC= 5.0 V, VI = VCC Pull-downs "on" VCC= 3.0 V, VI = VCC Pull-downs "on" VI = VCC VI = VCC VI = VCC
IIH
"H" input current
P00-P07, P10-P17, P30-P37
IIH IIH IIH IIL
"H" input current "H" input current "H" input current "L" input current
P20-P27, P40-P47, P50-P57, P60-P67, P70, P71 RESET XIN P00-P07, P10-P17, P34-P37, P40
IIL
"L" input current
P20-P27, P41-P47, P50-P57, P60-P67, P70-P77
A -5.0 "L" input current RESET -4.0 A "L" input current XIN Note 1 : When "1" is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. IIL IIL
45
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Symbol VRAM RAM hold voltage Parameter
(VCC = 2.5 to 5.5 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Test conditions When clock is stopped * High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors "off" A-D converter in operating * High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors "off" A-D converter stopped * Low-speed mode, VCC = 5 V, Ta 55C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" * Low-speed mode, VCC = 5 V, Ta = 25C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" * Low-speed mode, VCC = 3 V, Ta 55C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" * Low-speed mode, VCC = 3 V, Ta = 25C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" All oscillation stopped (in STP state) Output transistors "off" Ta = 25 C Ta = 85 C Min. 2.0 Limits Typ. Max. 5.5 Unit V
6.4
13
mA
1.6
3.2
mA
25
36
A
ICC
Power source current
7.0
14.0
A
15
22
A
4.5
9.0
A
0.1
1.0 10
A
46
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, 4 MHz f(XIN) 8 MHz, middle-/high-speed mode, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol - - tCONV RLADDER VREF IIA Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference input current Analog port input current Test conditions Min. Limits Typ. Max. 8 2 12.5 (Note) 12 VREF = 5 V 50 35 150 100 200 5.0 Unit Bits LSB s k A A
VCC = VREF = 5 V f(XIN) = 8 MHz
Note : When an internal trigger is used in middle-speed mode, it is 14 s.
47
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted.
Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT3 input "H" pulse width INT0 to INT3 input "L" pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input "H" pulse width (Note) Serial I/O clock input "L" pulse width (Note) Serial I/O input set up time Serial I/O input hold time Min. 2 125 45 40 200 80 80 80 80 800 370 370 220 100 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is "0" (UART).
TIMING REQUIREMENTS 2(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted.
Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT3 input "H" pulse width INT0 to INT3 input "L" pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input "H" pulse width (Note) Serial I/O clock input "L" pulse width (Note) Serial I/O input set up time Serial I/O input hold time Min. 2 125 45 40 500 230 230 230 230 2000 950 950 400 200 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 2 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is "0" (UART).
48
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS 1(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted.
Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C) Symbol twH(SCLK) twL(SCLK) td(SCLK-TXD) tv(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Limits Min. tc(SCLK)/2-30 tc(SCLK)/2-30 140 -30 30 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns
10 10
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2 : XOUT and XCOUT pins are excluded.
SWITCHING CHARACTERISTICS 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted. Extended operating temperature version : VCC = 3.0 to 5.5 V, Ta = -40 to -20C and VCC = 2.5 to 5.5 V, Ta = -20 to 85C)
Symbol twH(SCLK) twL(SCLK) td(SCLK-TXD) tv(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Min. tc(SCLK)/2-50 tc(SCLK)/2-50 -30 50 50 50 50 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns
350
20 20
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2 : XOUT and XCOUT pins are excluded.
Measurement output pin 100 pF Measurement output pin 100 pF 1 k
CMOS output
N-channel open-drain output (Note) Note : When bit 4 of the UART control register (address 001B16) is "1". (N-channel open-drain output mode)
Fig. 37 Circuit for measuring output switching characteristics (1)
49
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tc(CNTR) twH(CNTR) CNTR0,CNTR1
0.8VCC 0.2VCC
twL(CNTR)
twH(INT) INT0-INT3
0.8VCC 0.2VCC
twL(INT)
tw(RESET) RESET
0.2VCC 0.8VCC
tc(XIN) twH(XIN) XIN
0.8VCC 0.2VCC
twL(XIN)
tc(SCLK) tf SCLK
0.2VCC
twL(SCLK)
tr
0.8VCC
twH(SCLK)
tsu(RXD-SCLK) RXD td(SCLK-TXD) TXD
0.8VCC 0.2VCC
th(SCLK-RXD)
tv(SCLK-TXD)
50
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
*
* *
*
(c) 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Jan. 1998. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
3822 GROUP DATA SHEET
Revision Description Rev. date 980120
(1/1)

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